1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Related Art
Stacking technology to form a three-dimensional (3D) semiconductor integrated circuit (IC) has been developed to reduce the size of electronic appliances, increase stack density, and improve performance. The 3D stack package is a package in which a plurality of chips each having the same storage capacity are stacked, and is generally referred to as a stack chip package.
A stack chip package reduces fabrication costs using a simplified manufacturing process and enables mass production. However, a highly integrated stack chip package also has reduced interconnection space for electrical connections between chips.
In a conventional stack chip package, bonding pads of chips are electrically connected by bond wires to package pads disposed laterally with respect to the bonding pads of the chips. Therefore, space for accommodating the bond wires is necessary, and thus a unit package size is increased.
To resolve this issue, a stack chip package using a throughsiliconvia (TSV) has been suggested. In a TSV stack chip package, TSVs are formed through chips, and electrical connections between the stacked chips are made by vertically connecting the TSVs. A chip stacking method using TSVs according to the related art will be described in brief below.
FIGS. 1A to 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the related art.
Referring to FIG. 1A, holes (not shown) are formed in a wafer 10, and the holes are filled with a conductive metal to form TSVs 12 (The first TSV and the second TSV). At this time, the TSVs 12 (The first TSV and the second TSV) may have variations in depths due to various process variables.
Referring to FIG. 1B, a rear surface of the wafer 10 is subject to a back-grinding process to expose the TSVs 12. Some TSVs (The first TSVs) 12 having relatively shallow depths may not be exposed by the back grinding process, as indicated by “A” of FIG. 1B.
In order to solve this problem, the TSVs can be formed more deeply while maintaining the thickness by which a part the wafer is removed in the back-grinding process. However, in that case, the heights of the TSVs protruding out of the back surface of the wafer increases, causing device failures. On the other hand, if the rear surface of the wafer is excessively etched to expose the shallower TSVs, the wafer becomes thin and thus becomes vulnerable to cracks.